Timing Driven Gate Duplication for Delay Optimization

In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's rst component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and nal traversal is again from PO to PI in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We proved the problem of partitioning a fanout set between a node and it's replica to be NP-Complete 2]. Hence our proposed algorithm uses a heuristic for solving this problem which is optimal (locally) in speciic cases. We report delay improvements as high as 8% over highly optimized results generated by SIS (generated by using map-n 1-AFG option of the mapper). The potential of the algorithm is also demonstrated by reporting average delay improvements of around 26.2% after a good minimum delay technology mapper (map-n 1 option). The results show that along with other optimization strategies, gate duplication can be used for meeting the stringent delay constraints in todays multi-million gate designs.